Experiment 4
Made by/ Ahmed El Metwally
Understanding PCM Modulation
Welcome to the PCM Modulation Quiz! This quiz is designed to assess your knowledge and understanding of Pulse Code Modulation (PCM) and its applications in digital communication systems. With 30 well-crafted questions, you'll gain insights into the principles of PCM, its advantages, and its implementation.
Key Features:
- 30 Multiple Choice Questions
- Test Your Knowledge on PCM Concepts
- Learn about Encoding, Sampling, and Digital Signals
#1 PCM modulation is a kind of------ coding
A. binary
B. octal
C. source
D. hexadecimal
#2 The meaning of ----- coding is the conversion from analog signal to digital signal
A. octal
B. source
Hexadecimal
Binary
After converted to ------signal, it is easy for us to process the signal such as encoding, filtering the unwanted signal
A. analog
B. binary
C. octal
D. digital
#4 In communications systems, the quality of ----- signal is better than analog signal.
Digital
Binary
Octal
Good analog
#5 In PCM system, the digital signal can be easily ------ by using comparator.
Found
Filtered
Recovered
Determined
#6 In PCM modulation is commonly used in ------- and telephone transmission.
Analog
Digital
Video
Audio
#7 The main advantage is the PCM modulation only needs ------ sampling frequency
4 kHz
8 kHz
6 kHz
2 kHz
#8 In PCM modulator, the low-pass filter is used to remove the ------ in the audio signal.
Low frequency
High frequency
Noise
Unwanted
In PCM modulator, the audio signal will be ------ to obtain a series of sampling values.
Sampled
Encoded
Decoded
Selected
In PCM modulator, the signal will pass through ------- to quantize the sampling values.
A sampler
A LPF
An encoder
A quantizer
In PCM modulator, signal will pas through ------- to encode the quantization values
A decoder
An encoder
A sampler
A quantizer
In PCM modulator, the process of quantization can be achieved at one time by ---- converter.
DCA
DAC
ACD
ADC
#13 If the bits for PCM modulation is 3, then the quantization levels is ----
8
16
4
12
If the bits for PCM modulation is 4, then the quantization levels is ----
12
8
16
4
#15 The increasing of bits of PCM modulation will prevent the signal from -----
Detailed
Noise
Unwanted
Distortion
#16 The increasing of bits of PCM modulation will ------- the bandwidth.
Increase
Decrease
Enhance
Destroyed
In PCM modulator, we need to convert the ----- data to serial data, to satisfy the data format of PCM modulation.
Analog
Digital
Parallel
Binary
In PCM modulator, we need to convert the parallel data to ------ data, to satisfy the data format of PCM modulation
Series
Parallel
Diagonal
Serial
#19 In Figure (1), the name of the box no. 1 is -------
Quantizer
Sampler
LPF
Encoder
In Figure (1), the name of the box no. 2 is --------------
Sampler
LPF
Quantizer
Encoder
#21 In Figure (1), the name of the box no. 3 is --------------
Encoder
LPF
Sampler
Clock
#22 In Figure (1), the name of the box no. 4 is --------------
Quantizer
Encoder
LPF
Sampler
#23 In Figure (1), the name of the box no. 6 is --------------
LPF
Quantizer
C. Parallel to serial converter
Encoder
#24 In Figure (1), the name of the box no. 5 is --------------
LPF
Quantizer
C. Parallel to serial converter
Encoder
In the circuit shown in Figure (2), capacitors C1, C2, resistors R1, R2, R3, R4, and μA741 comprise a ------
Encoder
Sampler
Low-pass filter
Quantizer
#26 In the circuit shown in Figure (2), the voltage gain of the low pass filter is ------
1+R1/R4
1+R4/R1
1+R3/R2
1+R2/R3
In the circuit shown in Figure(2), if R2 = R3 = R and C1 = C2 = C, the cutoff frequency fo is equal to -------
R/(2Ï€ C)
2Ï€/(RC)
2Ï€ (R/C)
1/(2Ï€RC)
#28 The circuit shown in Figure (2) is used to implement -------- modulator.
ASK
PCM
FSK
PSK
In the circuit shown in Figure (2), the ------ signal will pass through R5, and input to pin 10, which is the inverting input terminal
Analog
Digital
Sampled
Received
In the circuit shown in Figure (2), master clock is the operation frequency of the system, which is ------- square wave frequency.
2048 Hz
2048 MHz
2048 kHz
4096 MHz
In the circuit shown in Figure (2), master clock of the system has a shape of ------- wave form.
Square
Triangular
Sawtooth
Sinusoidal
#31 In the circuit shown in Figure (2), the sampling frequency is ------
12 KHz
8 KHz
4 KHz
10 KHz
In the circuit shown in Figure (2), the sampler will sample the input audio signal in every - ------
0.1 ms
83 μs
0.125 ms.
25 ms
In the circuit shown in Figure (2), the sampling frequency is obtained by using the counter to divide the master clock frequency by -----
64
128
512
256
In the circuit shown in Figure (2), when FS0 = 0 and FS1 = 0, the output format is ------
8 bits CVSD
16-bits Linear
8-bits μ-Law
8-bits A-Law
In the circuit shown in Figure (2), when FS0 = 0 and FS1 = 1, the output format is ------
8-bits μ-Law
8 bits CVSD
8-bits A-Law
16-bits Linear
In the circuit shown in Figure (2), when FS0 = 1 and FS1 = 0, the output format is ------
8-bits A-Law
8-bits μ-Law
8 bits CVSD
16-bits Linear
In the circuit shown in Figure (1), when FS0 = 1 and FS1 = 1, the output format is ------
8-bits μ-Law
16-bits Linear
8 bits CVSD
8-bits A-Law
In early days, the communication system is mostly using the ----- signal to transmit signals.
Analog or digital
Digital
Analog
Analog and digital
Due to the ------ network communications, a lot of data or information is transmitted by using the technique of pulse wave modulation.
Analog
Digital
Analog or digital
Analog and digital
Pulse wave modulation can be used to transmit the ------ signal or data with a certain rate.
Digital audio
Analog video
Digital video
Analog audio
PAM, PWM and PPM modulations belong to ------ modulation
Analog
Digital
Analog and digital
Analog or digital
PCM modulations belong to ------ modulation
Analog
Digital
Analog and digital
Analog or digital
The PCM modulation is a real ------ signal that can be processed and stored by computer
Analog or digital
Analog and digital
Analog
Digital
For any pulse wave modulation, before modulating, the original continuous type signal must be ------
Encoded
Sampled
Quantized
Stored
The sampling rate of the sampling signal cannot be -----, or else the recovered signal will cause distortion
Very high
Moderate
Too high
Too low
If the sampling rate excesses double or more times of the maximum frequency of the signal, then the distortion level of the data recovery at the receiver will be the ------.
Minimum
Maximum
Bad
Good
If the frequency range of the audio signal is 40 Hz to 4 kHz, then the sampling signal frequency of the pulse wave modulation must be at least ------
4 kHz
12 KHz
8 kHz
10 kHz
Before the PCM signal sends into the PCM demodulator, we utilize a----- to recover the signal to the original level.
Quantizer
Encoder
LPF
Comparator
#12 Before demodulating PCM, the pulse wave signal will be converted to ----- digital signal.
Serial
Serial or parallel
Parallel
Serial and parallel
#13 In the block diagram shown in Figure (1), the box no. 1 is called ------
S/H
Decoder
Comparator
LPF
#14 In the block diagram shown in Figure (1), the box no. 2 is called ------
Decoder
Clock
S/H
Encoder
#15 In the block diagram shown in Figure (1), the box no. 3 is called ------
Clock
LPF
Decoder
S to P converter
#16 In the block diagram shown in Figure (1), the box no. 4 is called ------
Decode
Comparator
S/H
Clock
#17 In the block diagram shown in Figure (1), the box no. 5 is called ------
S to P converter
Decode
S/H
LPF
#18 In the block diagram shown in Figure (1), the box no. 6 is called ------
S/H
LPF
Decode
Comparator
#19 In PCM demodulator, the decoder will be n-bit ------
DAC
ADC
DCA
ACD
#20 In PCM demodulator, we utilize a ----- to remove the unwanted signal at the final part
HPF
BPF
LPF
Digital filter
#21 The circuit diagram shown in Figure (2) is called ------ demodulator.
ASK
PCM
FSK
PSK
#22 In the circuit diagram shown in Figure (2), the function of IC 1 is a -------
LPF
Positive amplifier
Inverted amplifier
Buffer
#23 In the circuit diagram shown in Figure (2), its input at ------
Pin 1
Pin 2
Pin 3
Pin 4
In the circuit diagram shown in Figure (2), the master clock is connected to -----
Pin 1
Pin 2
Pin 4
Pin 5
#25 In the circuit diagram shown in Figure (2), the value of its master clock is ----- kHz
512
1024
4069
2048
In the circuit diagram shown in Figure (2), the sample clock is connected to -----
Pin 1
Pin 2
Pin 3
Pin 4
In the circuit diagram shown in Figure (2), the value of its sample clock is ----- kHz
8
4
16
2
#28 In the circuit diagram shown in Figure (2), the encode mode selection is connected to -----
Pin 5
Pin 4
Pin 3
Pin 2
In the circuit diagram shown in Figure (2), the output signal is taken from -----
Pin 6
Pin 3
Pin 5
Pin 4
#30 In the circuit diagram shown in Figure (2), the input modulated signal is connected to ------
Pin 5
Pin 6
Pin 4
Pin 3
#31 From Figure (2), capacitor C3, resistors R3, R4, R5, and IC2 comprise a first order active ---
BPF
HPF
Matched filter
LPF
In the circuit diagram shown in Figure (2), the gain of IC2 is given by:
€“R5/R3
€“R3/R5
€“R5/R4
R4/R5
#33 In the circuit diagram shown in Figure (2), the cutoff frequency of IC2 is given by:
1/(2Ï€R4C3)
1/(2Ï€R5C3)
1/(2Ï€R3C3)
1/(2Ï€R3C2)
#1 In the wireless digital communication, it is ------ to transmit the digital data directly
Good
Easy
Bad
Not easy
In digital communication, it needs to pass through the modulator and modulate the ----- signal in order to send the signal effectively
Analog
Carrier
Digital
Actual
In the wireless digital communication, when we modulate the amplitude of the carrier this kind of modulation is called -------
PCM
FSK
ASK
PSK
Figure (1) shows the basic block diagram of ------- modulator.
FSK
ASK
PSK
PCM
In the basic block diagram shown if Figure (1), Unit 3 is represents --------
Information
Carrier signal
Digital signal
Analog signal
#6 In the basic block diagram shown if Figure (1), Unit 2 is represents --------
Digital signal
Analog signal
Information
Carrier signal
#7 In the basic block diagram shown if Figure (1), Unit 4 is represents --------
Buffer
Analog signal
Switch
Carrier signal
#8 In the basic block diagram shown if Figure (1), Unit 1 is represents --------
Analog signal
Switch
Buffer
Information
#9 In the basic block diagram shown if Figure (1), the output signal is taken from -----
Pin 1
Pin 2
Pin 3
Pin 1 or Pin 2
In Figure (1), when the data input is high, the output signal is coming from -------
Pin 2
Pin 1
Pin 3
Pin 1 or Pin 2
In Figure (1), when the data input is low, the output signal is coming from -------
Pin 2
Pin 1
Pin 3
Pin 1 and Pin 2
#12 The waveform shown in Figure (2) is the output of the ------- modulator.
PCM
ASK
FSK
PSK
#13 The digital data used to produce the modulate waveform shown in Figure (2) is ------
1001011
1100011
1101011
1101001
The circuit diagram shown in Figure (3) is used to implement ------- modulator
FSK
PCM
PSK
ASK
#15 The circuit diagram shown in Figure (3), resistors ------- comprise a voltage divided circuit.
R2, R3
R2, R5
R2, R4
R1, R3
In Figure (3), the main function of the voltage divided circuit is to let the ------ voltage waveform operates normally.
Offset
Positive
Composite
Negative
#17 In Figure (3), the first oscillation frequency is determined by resistor ------
R1
R2
R3
R4
#18 In Figure (3), the first oscillation frequency is determined by resistor connected at ------
Pin1
Pin2
Pin3
Pin4
#19 In Figure (3), the second oscillation frequency is determined by resistor ------
R1
R2
R3
R
#20 In Figure (3), the second oscillation frequency is determined by resistor connected at ------
Pin 5
Pin 3
Pin 1
Pin 2
#21 In Figure (3), the digital data is inputted at -------
Pin 4
Pin 3
Pin 1
Pin 2
#22 In Figure (3), the DC power supply is inputted at -------
Pin 5
Pin 6
Pin 4
Pin 3
#23 In Figure (3), the second oscillation frequency is equal to zero when ------is opened.
Pin 6
Pin 4
Pin 5
Pin 3
#24 In Figure (3), the output modulated signal is taken from -----
Pin 6
Pin 5
Pin 4
Pin 2
In the circuit diagram shown in Figure (4), the elements D1, R1, R2, R3, Q7 and Q8 comprise a -------
Dc voltage source
Dc current source
Ac current source
Ac voltage source
In the circuit diagram shown in Figure (4), the elements D1, R1, R2, R3, Q7 and Q8 comprise ------- to Q5 and Q6
Dc bias voltage
Ac bias current
Dc bias current
Ac bias voltage
#27 In the circuit diagram shown in Figure (4), the Q5 and Q6 comprise a ------- amplifier
Differential
Difference
Summing
Summer
#28 In the circuit diagram shown in Figure (4), the dc bias of Q1, Q2, Q3, and Q4 are ------
Q5 and Q7
Q5 and Q8
Q5 and Q6
Q8 and Q7
#29 In the circuit diagram shown in Figure (4), the data signal is inputted between -----.
Pin1 and Pin 2
Pin3 and Pin 4
Pin5 and Pin 6
Pin7 and Pin 8
#30 In the circuit diagram shown in Figure (4), The carrier signal is inputted between ------
Pin1 and Pin 2
Pin3 and Pin 4
Pin5 and Pin 6
Pin9 and Pin 10
In the circuit diagram shown in Figure (4), the gain of balanced modulator is inputted between -----
Pin3 and Pin 4
Pin5 and Pin 6
Pin7 and Pin 8
Pin9 and Pin 10
#32 In the circuit diagram shown in Figure (4), the bias adjustment is inputted between -----
Pin3 and Pin 4
Pin5 and Pin 6
Pin7 and Pin 8
Pin9 and Pin 10
#33 The circuit diagram shown in Figure (4) is called -------modulator.
Synchronous
Unbalanced
Asynchronous
Balanced
In digital communication systems, we need a----- to modulate the data to a high carrier frequency
Decoder
Modulator
Demodulator
Encoder
In digital communication systems, the main function of the receiver is to convert the digital signal back to the ------ signal.
Encoded
Modulated
Decoded
Modulating
#3 In digital communication systems, there are ------ methods to design the ASK demodulator.
Few
Many
Two
Three
#4 In the block diagram shown in Figure (1), Signal 1 is called ---------- ASK signal.
Analog
Modulating
Data
Modulated
#5 In the block diagram shown in Figure (1), Block 1 is called -------
Rectifier
LPF
Comparator
HPF
#6 In the block diagram shown in Figure (1), Block 2 is called -------
Comparator
HPF
LPF
Rectifier
#7 In the block diagram shown in Figure (1), Block 3 is called -------
HPF
Comparator
Rectifier
LPF
#8 In the block diagram shown in Figure (1), Signal 2 is called ----- signal
Amplified
Filtered
Compared
Rectified
#9 In the block diagram shown in Figure (1), Signal 3 is called ----- signal
Filtered
Rectified
Amplified
Compared
#10 In the block diagram shown in Figure (1), Signal 4 is called ----- signal
Amplified
Modulating
Filtered
Rectified
#11 When ASK signal pass through the------ we can obtain the positive half wave signal.
HPF
LPF
Comparator
Rectifier
#12 When the rectified ASK signal pass through the------ we can obtain an envelop detection.
LPF
Comparator
Rectifier
D.
#13 Figure (2), shows the circuit diagram of ------- ASK detector
Synchronous
Digital
Asynchronous
Analog
#14 In Figure (2), R1, R2 and μA741 comprise an -------
Rectifier
Non inverting amplifier
LPF
Inverting amplifier
#15 In Figure (2), D1 is the ------- diode.
Rectifying
Voltage regulator
Varactor
Full wave rectifier
In digital communication systems, we need a modulator to modulate the data to a high ----- frequency.
Analog
Signal
Carrier
Digital
#17 In Figure (2), R3 and C1 comprise ------- filter
A high pass
Low-pass
A band pass
Band stop
#18 In Figure (2), μA741, VR1, D2, R4, and C2 comprise -------
Comparator
LPF
Rectifier
Amplifier
#19 For the block diagram shown in Figure (3), its input signal is called ------ signal.
Analog
Modulated
Modulating
Information
#20 For the block diagram shown in Figure (3), Block 1 is called ------
Comparator
LPF
Voltage limiter
Square law detector
#21 For the block diagram shown in Figure (3), Block 2 is called ------
LPF
Voltage limiter
Square law detector
Comparator
#22 For the block diagram shown in Figure (3), Block 3 is called ------
Square law detector
Comparator
LPF
Voltage limiter
For the block diagram shown in Figure (3), Block 4 is called ------
Comparator
LPF
Voltage limiter
Square law detector
#1 In digital signal transmission, -------is used to recover the data signal.
HPF
LPF
The repeater
Encoder
During long haul transmission, the ------ part of the digital signal will easily attenuate
Low frequency
High frequency
Analog
Information
In digital communication systems, the signal has to be ------- before transmission.
Encoded
Modulating
Decoded
Modulated
In digital communication systems, ----- technique is to modulate the data signal to two different frequencies.
FSK
PSK
ASK
PCM
#5 In FSK technique, the data signal will be recovered based on the ----- different frequencies.
Five
Three
Two
Four
#6 The digital transmission technique shown in Figure (1) is belongs to ------
PCM
PSK
ASK
FSK
In Figure (1), when the data signal is 5 V, after the signal pass through the buffer, the switch S1 will ------
Open
Closed
Not connect
Not operate
#8 In Figure (1), switch S1 will closed, then the frequency of FSK signal is ------
F2 – f1
F2
F1 + f2
F1
In Figure (1), when the data signal is 5 V, after the signal pass through the buffer, the switch S2 will ------
Closed
Open
Not connect
Not operate
In Figure (1), switch S2 will closed, then the frequency of FSK signal is ------
F2 – f1
F2
F1 + f2
F1
#11 In Figure (1), switch S2 will opened, then the frequency of FSK signal is ------
F2 – f1
F2
F1 + f2
F1
In Figure (1), switch S1 will opened, then the frequency of FSK signal is ------
F2
F2 – f1
F1 + f2
F1
#13 In Figure (1), the difference between frequencies f1 and f2 has to be as ------ as possible.
Small
Suitable
Large
Big
#14 In Figure (1), the value of f1. is ------ Hz.
1370
870
2225
1725
#15 In Figure (1), the value of f2. is ------ Hz
870
2225
1370
1725
#16 In Figure (1), the frequency gap is equal to -------
2000
1500
1000
500
#17 In Figure (1), these two frequencies can be produced by using -----
LPF
CVO
VCO
HPF
#18 In Figure (1), the output signal frequencies are varied by the difference ------ levels
Voltage
Current
Resistance
Capacitance
#19 Varactor diode is mainly used for changing the -------- value of oscillator
Resistance
Inductance
Capacitance
Voltage
Varactor diode is a diode, which its ------- can be varied by adding a reverse bias to pn junction.
Capacitance
Inductance
Resistance
Voltage
In varactor diode, when reverse bias increases, the depletion region become -----
Suitable
Narrow
Not suitable
Wide
#22 In varactor diode, when reverse bias decreases, the depletion region become -----
Narrow
Suitable
Wide
Not suitable
#23 The circuit diagram shown in Figure (2) is used in --------
FSK demodulator
FSK modulator
ASK demodulator
FSK modulator
In Figure (2), the operation theory is to convert the voltage level of data signal to appropriate ------- level
Resistance
Current
Capacitance
Voltage
The circuit shown in Figure (2) is used as ------- converter.
Frequency to voltage
Voltage to current
Voltage to frequency
Capacitance
#26 In Figure (2), the Q1, Q2, R1, R2, R3, VR1 and VR2 comprise a ----- converter
Frequency
Voltage
Capacitance
Current
#27 In Figure (2), Q1 will operate as ------ gate
OR
AND
XOR
NOT
#28 In Figure (2), when the input signal of the base of Q1, is high, then Q1 will ------
Switch on
Open
Switch off
Short
#29 In Figure (2), when Q1 switch on, Q1 is -----
Switch on.
Open
Switch off
Short
#30 In Figure (2), if VR1 = 250 kΩ, VR2 = 5kΩ, the value of V1 = ------ V
9
10
8
11
#31 In Figure (2), if VR1 = 250 kΩ, VR2 = 5kΩ, the value of V2 = ------ V
9.865
9.789
9.254
9.967
#32 In Figure (2), if VR1 = 250 kΩ, VR2 = 5kΩ, the value of f1 = ------ Hz
595.238
600.587
589.238
610.568
#33 In Figure (2), if VR1 = 250 kΩ, VR2 = 5kΩ, the value of f2 = ------ Hz
598.548
610.587
605.126
565.236
#1 In FSK modulator, the ------- level of digital signal has been converted to frequency
Resistance
Current
Voltage
Reactance
#2 In FSK receiver, the ----- of digital signal should be converted back to voltage.
Frequency
Current
Voltage
Resistance
#3 PLL is a kind of automatic tracking system, which is able to detect the input signal ------
Reactance
Resistance
Voltage
Frequency
#4 The block diagram shown in Figure (1) is ----------- detector.
PCM
Asynchronous FSK
Synchronous ASK
PSK
#5 In Figure (1), the Signal 1 is a modulated -------- signal.
FSK
ASK
PSK
PCM
#6 In Figure(1), the integrated circuit IC 1 is a --------
Comparator
Buffer
Amplifier
Encoder
#8 In Figure (1), the central frequency of Filter 1 is equal to ------
ωC+ ωD
ωC- ωD
ωC/ ωD
ωD/ ωC
#9 In Figure (1), the central frequency of Filter 2 is equal to ------
ωC/ ωD
ωC+ ωD
ωC- ωD
ωD/ ωC
#10 In Figure (1), the Node 1 is a -------node.
Subtracting
Summing
Multiplying
Dividing
#11 In Figure (1), Signal 2 is a modulating -------
PSK
PCM
ASK
FSK
#12 The block diagram shown in Figure (2) is a---------- detector
PSK
Synchronous FSK
Asynchronous FSK
PCM
#13 In Figure (2), the Signal 1 is a modulated -------- signal.
ASK
PCM
PSK
FSK
#14 In Figure (2), the frequency of Signal 2 is equal to ------
ωC+ ωD
ωC- ωD
2(ωC+ ωD)
2(ωC- ωD)
#15 In Figure (2), the frequency of Signal 3 is equal to ------
2(ωC+ ωD)
2(ωC- ωD)
ωC- ωD
ωC+ ωD
#16 In Figure (2), the Node 1 is a ------- node.
Multiplying
Summing
Dividing
Subtracting
#17 In Figure (2), the Node 2 is a ------- node.
Summing
Dividing
Summing
Multiplying
#18 In Figure (2), the IC 1 is -------
Encoder
Amplifier
Buffer
Comparator
#19 In Figure (2), the Node 3 is a ------- node.
Summing
Multiplying
Subtracting
Dividing
#20 In Figure (2), the central frequency of Filter 1 is equal to ------
(ωC+ ωD)
2(ωC+ ωD)
2(ωC- ωD)
(ωC- ωD)
#21 In Figure (2), the central frequency of Filter 2 is equal to ------
2(ωC- ωD)
(ωC+ ωD)
2(ωC+ ωD)
(ωC- ωD)
#22 In Figure (2), the Filter 1 is a -------- filter
LPF
BPF
HPF
BSF
#23 In Figure (2), the Filter 2 is a -------- filter
HPF
BSF
LPF
BPF
#24 In Figure (2), when Signal 1 = 2cos(ωC+ ωD)t, the value of Signal 4 is ------
2cos(ωC- ωD)t
Cos2(ωC- ωD)t
Cos2(ωC+ ωD)t
2cos(ωC+ ωD)t
#25 In Figure (2), when Signal 1 = 2cos(ωC+ ωD)t, the value of Signal 5 is ------
Cos2(ωC+ ωD)t
2cos(ωC- ωD)t
Cos2(ωC- ωD)t
2cos(ωC+ ωD)t
#26 In Figure (3), the Block 1 has a name ------
Loop filter
Amplifier
Phase detector
VCO
#27 In Figure (3), the Block 2 has a name ------
VCO
Phase detector
Amplifier
Loop filter
#28 In Figure (3), the Block 3 has a name ------
Amplifier
VCO
Loop filter
Phase detector
#29 In Figure (3), the Block 4 has a name ------
Loop filter
Phase detector
Amplifier
VCO
#30 In Figure (3), the Signal 1 is changing with -------
Phase
Frequency
Amplitude
Voltage
#31 In Figure (3), the Signal 2 is changing with -------
Amplitude
Phase
Voltage
Frequency
#7 In Figure (1), the Filter 1 is a -------- filter
Band stop filter
HPF
LPF
BPF
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