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Quizzes > Computers & Technology > Computers & IT

CPU & Memory Quiz: Test Your Hardware Knowledge

Think you know 'what is CPU short answer'? Jump into the quiz!

Difficulty: Moderate
2-5mins
Learning OutcomesCheat Sheet
Paper art cutout CPU chip and memory sticks on sky blue background alongside quiz title text.

Use this CPU and memory quiz to check your hardware basics, from cores and cache to RAM types, speeds, and DDR generations. Practice at your pace, find gaps before an exam or PC build, and keep learning with hardware practice and parts practice .

What does CPU stand for?
Control Performance Unit
Computer Program Utility
Central Processing Unit
Central Program Unit
CPU stands for Central Processing Unit, which is the primary component of a computer that performs most of the processing inside the system. It executes instructions from programs and coordinates data flow between memory and peripherals. Essentially, it is the brain of the computer. .
Which component performs arithmetic and logic operations in a CPU?
Bus Interface Unit
Control Unit
Arithmetic Logic Unit (ALU)
Cache
The Arithmetic Logic Unit (ALU) is responsible for carrying out arithmetic operations like addition and logic operations like comparisons. It is a fundamental building block of the CPU. The ALU processes the data for tasks defined by program instructions. .
How is processor speed commonly measured?
Gigahertz (GHz)
Ohms (?)
Megabytes (MB)
Watts (W)
Processor speed is measured in hertz, commonly gigahertz (GHz), indicating billions of clock cycles per second. Higher GHz means a CPU can handle more cycles and potentially more instructions per second. This metric helps compare raw clock rates between CPUs. .
Which memory type is typically used for CPU cache?
DRAM
Flash
SRAM
EEPROM
Static RAM (SRAM) is used for CPU caches because it is faster and does not require periodic refresh like DRAM. SRAM uses bistable latches to store each bit, providing low latency. However, it is more expensive and less dense than DRAM. .
What is a core in a CPU?
The power regulation module
The CPU's heat spreader
A section of cache
An independent processing unit
A core is an independent processing unit within a CPU that can execute its own thread of instructions. Modern CPUs may have multiple cores to handle parallel tasks more efficiently. Each core includes its own ALU and control logic. .
Which bus connects the CPU to main memory?
USB bus
Memory bus
PCIe bus
Serial bus
The memory bus is the pathway that connects the CPU to main system memory (RAM). It carries address, data, and control signals. The width and speed of this bus affect memory throughput. .
What is the difference between bit and byte?
Bytes measure speed, bits measure size
1 byte = 8 bits
They are equivalent
1 bit = 8 bytes
A byte consists of 8 bits. Bits are binary digits (0 or 1) and are the smallest unit of data in computing. Bytes are used to represent larger data values and are common in memory and storage metrics. .
What does DDR stand for in DDR SDRAM?
Dual Dimension Register
Direct Dual Range
Digital Dynamic RAM
Double Data Rate
DDR stands for Double Data Rate, meaning data is transferred on both the rising and falling edges of the clock signal. This effectively doubles the data throughput compared to single data rate SDRAM. DDR technology has evolved through multiple generations (DDR2, DDR3, DDR4, DDR5). .
Which CPU feature allows one physical core to appear as two logical cores?
SpeedStep
QuickPath Interconnect
Hyper-Threading
Turbo Boost
Hyper-Threading is Intel's simultaneous multithreading implementation that allows a single physical core to handle two threads concurrently. It improves parallelism and can boost performance in multithreaded tasks. Other vendors have similar technologies under different names. .
In dual-channel memory mode, how should DIMMs be installed?
One in the first slot only
Opposite diagonals on the motherboard
In matching color-coded slots
In any two slots
Dual-channel mode requires installing identical DIMMs in the motherboard's matching color-coded slots. This configures two separate memory channels for parallel access, doubling bandwidth. Manufacturers document slot pairing in the manual. .
What is instruction pipelining?
Overlapping instruction execution stages
Encrypting instruction streams
Processing one instruction at a time
Storing instructions in cache
Instruction pipelining splits instruction processing into stages (fetch, decode, execute, etc.) and overlaps them for multiple instructions. This increases instruction throughput and CPU efficiency. Hazards such as data dependencies must be managed. .
Which register holds the address of the next instruction to execute?
Program Counter (PC)
Instruction Register (IR)
Stack Pointer (SP)
Accumulator (ACC)
The Program Counter (PC) register contains the memory address of the next instruction to be fetched and executed. After each instruction fetch, the PC is updated to point to the following instruction. It is essential for sequential program flow. .
What is the purpose of the Translation Lookaside Buffer (TLB)?
Cache recent virtual-to-physical address translations
Store L1 cache lines
Manage CPU voltage
Hold process thread states
The TLB is a cache that holds recent virtual-to-physical address mappings for fast virtual memory translation. It reduces the need to consult slower page tables in main memory. A TLB miss incurs additional latency to retrieve the mapping. .
What effect does increasing DRAM CAS latency have?
Increases memory access delay
Enhances virtual memory swap
Reduces CPU clock speed
Lowers physical memory capacity
CAS (Column Address Strobe) latency is the delay between a memory read command and when data is available. Higher CAS latency means additional clock cycles before data access completes, increasing overall memory latency. Lower CAS latency is desirable for faster memory performance. .
Which cache coherence protocol uses the states Modified, Exclusive, Shared, and Invalid?
MESI
MESIF
MOESI
MSI
The MESI protocol defines four cache line states: Modified, Exclusive, Shared, and Invalid, to maintain coherence across CPU cores. It ensures updates propagate correctly in multi-core systems. MESI is widely used in modern processor architectures. .
What is out-of-order execution in CPUs?
Scheduling instructions at compile time
Encrypting instructions before execution
Executing instructions as operands become ready, not strictly in program order
Running threads on separate cores
Out-of-order execution allows a CPU to process instructions as soon as their operands are available, rather than strictly following program sequence. This increases resource utilization and throughput. Reordering is transparent to the program due to dependency tracking. .
Which of these is a primary difference between RISC and CISC architectures?
CISC cannot pipeline instructions
RISC supports only 8-bit data
RISC uses simpler instructions with fixed length
CISC has no microcode
RISC (Reduced Instruction Set Computer) architectures employ a small set of simple, fixed-length instructions to enable efficient pipelining. CISC (Complex Instruction Set Computer) offers more complex instructions, often variable in length. Modern CPUs blur these lines, but basic RISC design remains simpler. .
What is non-uniform memory access (NUMA)?
A type of RAID for memory modules
A mode to synchronize caches
A dual-channel configuration
A memory design where access time depends on memory location relative to processor
NUMA architectures divide memory into nodes, each with local and remote memory relative to a CPU. Access to local memory is faster than remote memory. NUMA improves scalability in multi-socket systems but requires OS support for optimal allocation. .
Which technique reduces branch penalty in pipelined CPUs?
Cache prefetching
Voltage scaling
Branch prediction
Out-of-order retirement
Branch prediction estimates the outcome of conditional branches to pre-load the correct instruction path, reducing pipeline stalls. Accurate predictors significantly improve performance in deep pipelines. Mispredictions incur penalty but modern designs minimize their impact. .
What is the primary benefit of a multi-level cache hierarchy?
Balancing access speed and capacity across levels
Increasing DRAM refresh rates
Eliminating all cache misses
Synchronizing CPU cores
Multi-level caches use small, fast levels (L1) and larger, slower levels (L2/L3) to optimize hit rates and reduce average access time. Frequently accessed data stays closer to the CPU, while less critical data resides deeper. This hierarchy balances performance and die area. .
Which factor most directly affects DRAM bandwidth?
CAS latency
Socket type
Data rate and bus width
Number of CPU cores
DRAM bandwidth is determined by the data transfer rate (e.g., DDR frequency) and the width of the memory bus (bits per transfer). Together these define the maximum data throughput. Latency affects access delay but not peak bandwidth. .
What vulnerability class exploits speculative execution to leak data across security boundaries?
Meltdown
Blue Pill
Rowhammer
Spectre
Spectre vulnerabilities leverage speculative execution and branch prediction to access privileged memory contents and then leak them via side channels. It affects many modern CPU architectures. Mitigations involve software barriers and microcode updates. .
Which of these best describes simultaneous multithreading (SMT)?
Allowing multiple threads to issue instructions to a core's execution units in the same cycle
Assigning separate L1 caches per thread
Swapping threads during context switches
Running each thread on a different physical core
SMT enables a single physical core to execute instructions from multiple threads simultaneously by sharing execution resources. This boosts utilization when one thread stalls. Intel's Hyper-Threading is an example of SMT. .
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Study Outcomes

  1. Understand CPU fundamentals -

    After completing the quiz, you will be able to summarize the core functions of a CPU and confidently answer questions like "what is CPU short answer."

  2. Differentiate memory types -

    You will be able to distinguish between various memory modules (RAM, cache, ROM) and explain their roles in system performance.

  3. Analyze CPU and memory interactions -

    You will be able to describe how processors and memory work together to execute programs efficiently.

  4. Apply memory management concepts -

    You will be able to identify common memory management techniques and troubleshoot basic memory issues.

  5. Evaluate hardware knowledge -

    You will be able to assess your hardware skills through scored feedback and pinpoint areas for further learning.

  6. Recall computer hardware trivia -

    You will be able to answer CPU & memory quiz questions with confidence and use trivia to reinforce your knowledge.

Cheat Sheet

  1. CPU: What It Is & Why It Matters -

    The CPU (central processing unit) is the "brain" of a computer, executing instructions from programs in cycles. For a short answer, it interprets and processes data to perform tasks, from simple math to complex simulations. Remember: without a CPU, nothing moves - think "Central Power Unit" as a mnemonic for its core role.

  2. Clock Speed, Cores & Threads -

    Clock speed (measured in GHz) indicates how many cycles a CPU can perform per second, while cores and threads determine how many tasks run in parallel. More cores and threads mean better multitasking, so a quad-core CPU with hyper-threading can handle eight threads at once. When studying for your cpu and memory quiz, compare MHz vs. GHz and note that higher isn't always better without sufficient cores and thread support.

  3. RAM vs. ROM Essentials -

    RAM (volatile memory) holds data for active processes, whereas ROM (non-volatile) stores firmware that boots your system. In memory quiz questions, recall that DDR memory generations (DDR3, DDR4, DDR5) boost bandwidth and lower latency with each iteration. A handy trick: "Volatile RAM Drops," meaning the data drops when power stops, unlike ROM's steady read-only state.

  4. Memory Hierarchy & Cache Strategies -

    Systems use a hierarchy - registers, L1/L2/L3 cache, main memory, then storage - to balance speed and size. Caches use policies like LRU (Least Recently Used) to keep frequently accessed data close to the CPU, cutting down on costly main-memory fetches. For cpu memory trivia, remember: L1 is fastest but smallest, while L3 is slower but much larger.

  5. Performance Formula: CPI, IC & Clock Rate -

    CPU time = (Instruction Count × CPI) ÷ Clock Frequency, where CPI is cycles per instruction. By reducing instructions or CPI, or boosting frequency, you improve performance - an essential concept in any computer hardware quiz. Practice with real examples: if IC=1e9, CPI=2, and frequency=2GHz, then CPU time = (1e9×2)/2e9 = 1 second.

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