Logic Circuits

A ripple counter's speed is limited by the propagation delay of _______.

Only circuit gates

Each flip-flop

All flip-flops and gates

The flip-flops only with gates

A single transistor can be used to build which of the following digital logic gates

AND

NOT

NAND

The time needed for an output to change as the result of an input change is known as:

Rise time

Fanout

Noise immunity

Propagation delay

The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):

NOR Gate

OR gate

AND gate

NOT Gate

Logically, the output of a NOR gate would have the same Boolean expression as a(n):

OR gate immediately followed by an INVERTER

NAND gate immediately followed by an INVERTER

AND gate immediately followed by an INVERTER

NOR gate immediately followed by an INVERTER

If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n):

NAND

NOR

AND

A digital logic device used as a buffer should have what input/output characteristics?

High input impedance and high output impedance

Low input impedance and lowoutput impedance

High input impedance and low output impedance

Low input impedance and high output impedance

Which statement below best describes a Karnaugh map?

Variable complements can be eliminated by using Karnaugh maps

A Karnaugh map can be used to replace Boolean rules.

The Karnaugh map eliminates the need for using NAND and NOR gates

It is simply a rearranged truth table.

Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?

OR gates only

AND gates, OR gates, and NOT gates

OR gates and NOT gates

AND gates and NOT gates

Which of the following summarizes the important features of emitter-coupled logic (ECL)?

Poor noise immunity, positive supply voltage operation, good low-frequency operation, and low power

Negative voltage operation, high speed, and high power consumption

Good noise immunity, negative logic, high frequency capability, low power dissipation, and short propagation time

Slow propagation time, high frequency response, low power consumption, and high output voltage swings

What is one disadvantage of an S-R flip-flop?

It has a RACE condition.

It has only a single output.

It has no clock output.

It has no ENABLE output.

Select one of the following statements that best describes the parity method of error detection.

Parity checking is capable of detecting and correcting errors in transmitted codes.

Parity checking is best suited for detecting single-bit errors in transmitted codes.

Parity checking is not suitable for detecting single-bit errors in transmitted codes.

The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as _______.

A Karnaugh map

The commutative law of addition

The associative law of multiplication

DeMorgan`s second theorem

A TTL totem pole circuit is designed so that the output transistors are _______.

Providing voltage regulation

Never on together

Providing phase splitting

Always on together

The problem of interfacing IC logic families that have different supply voltages can be solved by using a ______.

Translator

Tri-state shifter

Level-shifter

Level-shifter or translator

Which of the following is correct for a gated D-type flip-flop?

The output complement follows the input when enabled.

The output toggles if one of the inputs is held HIGH.

The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.

Only one of the inputs can be HIGH at a time.

The commutative law of addition and multiplication indicates that:

The way we OR or AND two variables is unimportant because the result is the same

The factoring of Boolean expressions requires the multiplication of product terms that contain like variables

An expression can be expanded by multiplying term by term just the same as in ordinary algebra

We can group variables in an AND or in an OR any way we want

What input values will cause an AND logic gate to produce a HIGH output?

At least one input is HIGH

All inputs are HIGH.

At least one input is LOW

All inputs are LOW

What is the significance of the J and K terminals on the J-K flip-flop?

There is no known significance in their designations.

All of the other letters of the alphabet are already in use.

The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.

The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.

The output will be a LOW for any case when one or more inputs are zero in a(n):

AND gate

NAND gate

NOT gate

OR gate

What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?

PIPO

PISO

SIPO

SISO

The systematic reduction of logic circuits is accomplished by _______.

Symbolic reduction

Using a truth table

Using Boolean algebra

TTL logic

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