Datorteknik
Test Your Knowledge in Computer Engineering
Challenge yourself with this engaging quiz designed for enthusiasts of computer engineering and architecture. Test your understanding of topics ranging from assembly language to memory systems.
Key Features:
- Multiple choice format for easy participation
- Covers a wide range of topics in computer technology
- Perfect for students and professionals alike
The zero flag is set when we execute the instruction SUB R1, R2, R3
True
False
MIMD is one of the categories in Flynn's taxonomy.
True
False
Operand 2 in the arithmetic instructions can be either a register or a small immediate value.
True
False
There is no problem to use R0 in both your program and an interrupt handler.
True
False
A cache is usually implemented using a dynamic random access memory.
True
False
Before executing the interrupt handler all registers are automatically saved on the stack.
True
False
SysTick can use MCK/3 for operation.
True
False
A 5 stage pipeline can achieve more than 5 times speedup.
True
False
LR must be pushed to the stack at the begining of any recursive function.
True
False
TC can count down.
True
False
A DRAM cell consists of 6 transistors.
True
False
In the capture mode of TC, PIOA and PIOB are configured as outputs.
True
False
Memory-mapped I/O can use load and store instructions to deal with the I/O
True
False
Consider the following cache: index V Tag Data 000 0 001 0 010 0 011 0 100 0 101 0 110 0 111 0 If the CPU tries to access location 32, then a miss will be generated.
True
False
Polling wastes both CPU energy and performance.
True
False
If R0 and R1 are UQ16.16 numbers then their difference can be computed in assembly using the SUB instruction.
True
False
The resolution of floating point numbers using IEEE754 improves as the number gets smaller in magnitude.
True
False
A VLIW computer depends on the compiler to achieve parallelism during run time.
True
False
Non-vectored interrupts are the preferred design choice in most modern processors.
True
False
If the number 0xFFFF8111 is a single precision floating point, then it is a normalized number.
True
False
Consider the following cache (all values in the cache are shown in binary): index V Tag Data 000 0 001 0 010 0 011 0 100 0 101 0 110 1 1100 111 0 If the CPU tries to access location 103 in decimal, then a hit will be generated.
True
False
SISD is one of the categories in Flynn's taxonomy.
True
False
RTT can generate an interrupt that wakes up the processor.
True
False
There is no problem to use R5 in both your program and an interrupt handler.
True
False
MISD is a kind of instruction level parallelism.
True
False
ADDRESS 0x20007000 00 AF 69 07 92 87 AF 4C 5B E2 1C FC C9 D4 5A 81 0x20007010 7D 6A BC DE 10 57 8F 00 11 4A 5E AD DC 4F 88 92 0x20007020 DE 65 82 7A 0F 67 81 12 34 25 61 AE CD EB B5 3E Iterate the following program: Base_Address EQU 0x200070018 LDR R0, =Base_Address LDM R0!, {R1,R2} EOR R1, R2 EOR R2, R1 EOR R1, R2 What is its function?
Assigning the value of R1 by the value of R2
XOR R1 by R2
Negating the values of R1 and R2
Swapping the values of R1 and R2
What is the octal representation of the decimal value 2963
1422
1256
234F
5623
Which memory addressing mode is used in the following instruction? STR R4, [R1, # 8]!
Direct Addressing Mode
Pre-Indexed Addressing Mode
Offset Addressing Mode
Post-Indexed Addressing Mode
Select an equivalent instruction for: POP {R4-R9}
LDM SP, {R4-R9}
LDR SP!, {R4-R9}
LDM SP!, {R4-R9}
LDR SP, {R4-R9}
Select an equivalent instruction for: PUSH {R5, R9}
STM SP, {R5, R9}
STR SP!, {R5, R9}
STR SP, {R5, R9}
STM SP!, {R5, R9}
The Overflow flag is used for :
Signed operations
Unsigned operations
Both signed and unsigned operations
All of the above
ADDRESS 0x20007000 00 AF 69 07 92 87 AF 4C 5B E2 1C FC C9 D4 5A 81 0x20007010 7D 6A BC DE 10 57 8F 00 11 4A 5E AD DC 4F 88 92 0x20007020 DE 65 82 7A 0F 67 81 12 34 25 61 AE CD EB B5 3E Iterate the following program : Base_Address EQU 0x20007014 LDR R0, =Base_Address LDR R1, [R0], #4 What is the value stored in R0 and R1, respectively?
0x20007004 , 0x0769AF00
0x20007014 , 0x008F5710
0x4CAF8792, 0x20007000
0x20007008 , 0x4CAF8792
A 2-way set associative cache that includes 4 blocks has a set size of
4
16
2
8
What reload value is needed to have the SysTick interrupt trigger every 0.25 seconds when using 12MHz clock?
8999999
7999999
2999999
11999999
Which register is used to enable SysTick?
SYSTICK_CTRL
SYSTICK_VAL
NVIC_ISER0
SYSTICK_LOAD
Which memory addressing mode is used in the following instruction? STR R5, [R7]
Post-Indexed Addressing Mode
Direct Addressing Mode
Offset Addressing Mode
Pre-Indexed Addressing Mode
If SCK is 32768Hz, what is the prescaler value needed to make RTT generate an interrupt every 0.25 second?
65536
0x2000
16384
32768
What does the following assembly code do? LDR R0, =PMC_PCDR0 LDR R1, =0x00000800 STR R1, [R0]
It disables the peripheral with PID=11
It enables the clock for peripheral with PID=11
It disables the peripheral with PID=13
It enables the clock for the peripheral with PID=13
What does the instruction "POP {R5}" correspond to?
SP = SP + 4, and then R5 = memory [SP]
R5 = memory [SP], and then SP = SP - 4
SP = SP - 4, and then R5 = memory [SP]
R5 = memory [SP], and then SP = SP + 4
If you keep checking if an event occurred in your code, then you are using a technique that is called
Polling
Exceptions
Interrupts
Faults
In a directly mapped 32 blocks cache, a main memory block of address 123, has an index of Note: All numbers all represented in decimal
26
27
10
3
ADDRESS 0x20007000 00 AF 69 07 92 87 AF 4C 5B E2 1C FC C9 D4 5A 81 0x20007010 7D 6A BC DE 10 57 8F 00 11 4A 5E AD DC 4F 88 92 0x20007020 DE 65 82 7A 0F 67 81 12 34 25 61 AE CD EB B5 3E 5 Iterate the following program : Base_Address EQU 0x20007018 LDR R0, =Base_Address LDMIA R0!, {R1 - R2} What is the value stored in R0, R1 and R2, respectively?
0x20007024 , 0x92884FDC, 0x7A8265DE
0x20007018 , 0xAD5E4A11, 0x92884FDC
0x20007020 , 0x92884FDC, 0x7A8265DE
0x20007020 , 0xAD5E4A11, 0x92884FDC
Which register is used to disable the watchdog timer?
WDT_MR
PIO_ODR
WDT_CR
PMC_PCDR0
What is the 8-bit two's complement representation of the decimal value +113?
10110101
01110001
10111100
01110101
Considering a direct mapped 8 block cache, the tag value of block 127 in the main memory is Note: all numbers are in decimal.
7
111
15
3
What does the instruction "PUSH {R5}" correspond to?
SP = SP + 4, and then memory [SP] = R5
Memory [SP] = R5, and then SP = SP - 4
SP = SP - 4, and then memory [SP] = R5
Memory [SP] = R5, and then SP = SP + 4
ADDRESS 0x20007000 00 AF 69 07 92 87 AF 4C 5B E2 1C FC C9 D4 5A 81 0x20007010 7D 6A BC DE 10 57 8F 00 11 4A 5E AD DC 4F 88 92 0x20007020 DE 65 82 7A 0F 67 81 12 34 25 61 AE CD EB B5 3E What is the stored value at the address 0x2000701C in case of Big Endian?
0xAD 5E 4A 11
0xDC 4F 88 92
0x11 4A 5E AD
0x92 88 4F DC
If the miss rate is 0.1, the cache access time is 1 and the miss penalty is 100, then the average memory access time is …………… cycles.
101
10.9
1.9
90.1
Which value should be placed in SYSTICK_CTRL in order to disable SysTick?
0x7
0xB
0x3
0x0
The Carry flag is used for:
Signed operations
Unsigned operations
Both signed and unsigned operations
All of the above
What does the instruction "POP {R5-R7}" correspond to?
SP = SP - 4, R5 = memory [SP], then SP = SP - 4, R7 = memory [SP]
R7 = memory [SP], SP = SP - 4, then, R6 = memory [SP], SP = SP - 4, then, R5 = memory [SP], SP = SP - 4
SP = SP + 4, R5 = memory [SP], then SP = SP + 4, R7 = memory [SP]
R5 = memory [SP], SP = SP + 4, then, R6 = memory [SP], SP = SP + 4, then, R7 = memory [SP], SP = SP + 4
An instruction that can be used to return from an Interrupt (exception) is
BX LR
MRS R0, LR
MSR R0, LR
B LR
ADDRESS 0x20007000 00 AF 69 07 92 87 AF 4C 5B E2 1C FC C9 D4 5A 81 0x20007010 7D 6A BC DE 10 57 8F 00 11 4A 5E AD DC 4F 88 92 0x20007020 DE 65 82 7A 0F 67 81 12 34 25 61 AE CD EB B5 3E Iterate the following program : Base_Address EQU 0x20007024 LDR R0, =Base_Address 7 LDR R1, [R0, #4] What is the value stored in R0 and R1, respectively?
0x20007024 , 0x1281670F
0x4CAF8792, 0x20007000
0x20007024 , 0xAE612534
.0x20007000 , 0x4CAF8792
What does the instruction "PUSH {R5-R7}" correspond to?
Memory [SP] = R5, SP = SP - 4, then, memory [SP] = R7, SP = SP - 4.
Memory [SP] = R5, and then SP = SP + 4, then, memory [SP] = R7, and then SP = SP + 4
SP = SP + 4, memory [SP] = R5, then, SP = SP + 4, memory [SP] = R6, then, SP = SP + 4, memory [SP] = R7.
SP = SP - 4, memory [SP] = R7, then, SP = SP - 4, memory [SP] = R6, then, SP = SP - 4, memory [SP] = R5.
Consider the following IEEE754 single precision floating number 0x70600000.
-1.75 * 10^224
1.75 * 2^97
1.75 * 10^97
1.75 * 2^224
A RISC processor has reduced cycles per instruction
True
False
Assembly instructions are independent from the CPU architecture.
True
False
An assembly instruction consists of two parts an opcode and and operand.
True
False
The number of instructions per program is larger in a CISC computer.
True
False
Adding the suffux S to bitwise logic instructions (e.g. AND, ORR, etc.) will set the corresponding flag in the PSR register (NVZC) according to the final result.
True
False
Load-Store Instructions transfer data between registers.
True
False
The two instructions B and BAL are equivqlent to each other.
True
False
For the comparison instructions (CMP, TEQ, etc.) to update the condition flags they require adding suffix S at the end of it.
True
False
Select the code equivalent for the following instruction: CBZ R0, label
CMP R0, #0x0 BEQ label
CMP R0, #0x0 BNE label
CMP R0, #0x0 BAL label
CMN R0, #0x0 BEQ label
The CMP instruction is equivalent to :
SUBS
SUB
ADDS
ADD
PUSH {R7} is the equivalent to as LDM SP!, {R7}.
True
False
The Stack Pointer (SP) is a special register that is used to identify the bottom of the stack.
True
False
A Stack is a form of storage space in memory where reading and writing in it follows Last In First Out (LIFO) algorithm.
True
False
To enable the clock signal on port C, we write [blank 1] in the register [blank 2]
0xC0, PMC_PCER0
0x2000, PMC_PCSR0
0x13, PMC_PCER0
0x2000, PMC_PCER0
To turn on the LEDs connected to bits 6 and 7 on port C. We write the value [blank 1] to the register [blank 2]
0xFFFFFF3F, PIOC_SODR
0xFFFFFF3F, PIOC_CODR
0xC0, PIOC_SODR
0xC0, PIOC_CODR
To turn off the LEDs connected to bits 6 and 7 on port C. We write the value [blank 1] to the register [blank 2]
0xFFFFFF3F, PIOC_SODR
0xFFFFFF3F, PIOC_CODR
0xC0, PIOC_SODR
0xC0, PIOC_CODR
Select the correct missing instruction. To disable the watchdog timer, we write the value 0x8000 to the register WDT_MR using the following assembly code LDR R0,=0x8000 LDR R1, =WDT_MR [blank 1] ; missing instruction
LDR R0,[R1]
MOV R0,R1
STR R0, [R1]
MRS R0,R1
Select all correct instructions that can set the bit 7 in R0 and make all other bits 0.
MOV R0,#0x80
LDR R0, =0x80
LDR R0, [0x80]
MOV R0, #(1<<7)
In order to successfully use interrupts you need to configure
The CPU
The NVIC moduleThe NVIC module
The hardware module/peripheral to generate the interrupt
The assembler
An interrupt handler is called automatically when an interrupt happens.
True
False
Before executing the interrupt handler only R0-R3 are saved on the stack.
True
False
Timers are special hardware units that helps the CPU deal with time.
True
False
The following is correct about SysTick
It is 32 bits
It counts down
It can generate interrupts at every tick
It generates interrupts when it reaches 0.
SysTick can use MCK/16 for operation.
True
False
What reload value is needed to have the SysTick interrupt trigger every 0.5 seconds when using 12MHz clock?
5999999
11999999
2999999
6000000
What is true about RTT?
It is 32 bits
It counts up
It can generate an interrupt at every tick
It can generate an interrupt at a programmed Alarm value
If SCK is 32768Hz, what is the prescaler value needed to make RTT generate an interrupt every 0.5 second?
16384
65536
32768
0x8000
RTC can generate an interrupt that wakes up the processor.
True
False
TC can use 5 different internal clock sources or 3 external clock sources.
True
False
IF the number 0x0000ABCD is a single precision floating point, then it is a normalized number.
True
False
The resolution of floating point numbers using IEEE754 is constant.
True
False
Cortex M3 has a floating point unit that handles floating point arithmetic.
True
False
If R0 and R1 are UQ16.16 numbers then their sum can be computed in assembly using the ADD instruction.
True
False
Flash memories are volatile memories.
True
False
A direct mapped cache can be considered as a "Blank"-way set associative memory.
1
4
8
2
Different memories have differen properties. Registers are [blank 1] and [blank2]. While Hard disk is [blank 3] and [blank 4]
Faster, cheaper, slower, more expenive
Slower, cheaper, faster, more expensive
Slower, more expensive , faster, cheaper
faster, more expensive , slower, cheaper
The most flexible cache mapping method is the Blank 1
Fully associative mapping
Direct mapping
N-way set associative
In cache direct mapping, replacment algorithm is required.
True
False
Translation Lookaside Buffer (TLB) is a special cache for storing the page table.
True
False
Thrashing happens when the page-fault rate is extremly low.
True
False
Pipelining is a type of data level parallelism (DLP).
True
False
SIMD is a kind of data level parallelism.
True
False
A computer with a faster clock will always perform better.
True
False
Multi-threading cannot be done in a uniprocessor system.
True
False
A 3 stage pipeline can achieve up to 3 times speedup.
True
False
Flynn's taxonomy has four categories: SISD, SIMD, MISD, and MIMD.
True
False
{"name":"Datorteknik", "url":"https://www.quiz-maker.com/QPREVIEW","txt":"Challenge yourself with this engaging quiz designed for enthusiasts of computer engineering and architecture. Test your understanding of topics ranging from assembly language to memory systems.Key Features:Multiple choice format for easy participationCovers a wide range of topics in computer technologyPerfect for students and professionals alike","img":"https:/images/course4.png"}