IOSPD exam - Buses
IOSPD Exam - Buses Quiz
Test your knowledge on various bus architectures used in computing systems with our comprehensive IOSPD Exam Quiz. This quiz covers a broad spectrum of topics including PCI Express, I2C, SPI, and VME buses.
- 16 engaging questions
- Multiple-choice format
- Ideal for certification preparation
A PCI Express link:
- Requires at least four wires.
- May contain any number of communication lanes.
- Consists of bidirectional channels.
- Can contain up to 32 communication lanes.
- Utilizează o frecvență a semnalului de ceas care este setata în mod automat de sistemul de operare.
- Conține benzi de comunicatie, fiecare fiind implementată ca un singur canal de comunicatie bidirectional.
PCI Express interrupts:
- In legacy mode, are signaled by devices with the INTA# … INTD# interrupt request signals.
- In legacy mode, use special messages that act as interrupt request signals.
- In legacy mode, they use special messages that indicate signal activation for interrupt requests.
- In native mode, are signaled with memory write transactions.
- In native mode, they are signaled through message transitions specific to PCI Express bus.
PCI Express bus:
- It is software compatible with PCI parallel bus.
- Permits only point-to-point connections.
- It does not require synchronization between signals, compared to PCI parallel bus.
The parallel PCI bus:
- Uses a priority-based arbitration algorithm.
- Requires to use either a series or a parallel bus termination.
- Does not require extra clock cycles for arbitration procedure.
With the I2C bus:
- Full duplex communication is NOT possible.
- Duplex communication is NOT possible.
- Each device has a unique address assigned to it.
- The device address and the data direction is transmitted after START condition.
- Transfer rate is reduced compared to SPI bus.
- No acknowledge bit sent.
- Each data transfer begins with a START bit and is followed by a STOP bit.
With the SPI bus:
- Data is transferred in both directions simultaneously.
- Advantages are achieved when there is a single slave device.
- It is more efficient for applications that require duplex communication.
- It does NOT allow device addressing through a unique/specific address for each device.
- An acknowledge bit is sent after each data word.
- Transfer rates are similar to those of the I2C bus.
- It is more advantageous for systems with many/more “slave” devices.
Select the cases when using the SPI bus is more advantageous than using the I2C bus:
- The system contains several slave devices.
- The data rate required is 5 megabits per second.
- The word size is 12 bits.
USB 3.2 doubles the transfer rate of USB 3.1 by:
- Operating on two lanes.
- Adding a new communication lane.
- Using a more efficient encoding compared to version 3.1.
- Doubling the clock frequency.
USB 3.0 version
- Adds 2 unidirectional differential channels in addition to the existing differential channel (from 2.0 version).
- Replaces the existing differential channel with 2 unidirectional channels.
- Adds a bidirectional (duplex) differential channel to the existing differential channel.
With isochronous transfers on the USB bus:
- Data is always delivered/provided on time.
- There can appear losses in data stream/flow.
- Provided data is always correct.
- The transfer rate depends on other activities on the bus.
- Transmission errors are corrected by retransmission.
VME64x bus uses a modified protocol which:
- Uses both fronts (edges) of strobe and ACK signals for data transfer.
- Is a source synchronous protocol.
- Uses both clock signal fronts (edges) for data transfer.
VME64x bus:
- Allows adding and eliminating extension modules without shutting down the system.
- Uses 2eVME (Double-edge VME) protocol at which data transfer takes place at both clock edges.
- Can use extension modules with convection cooling, with special guides of boards that transfer the heat to the chassis.
VXS Modules (VMEbus Switched Serial):
- Uses switching boards that have point to point connections with the rest of the boards.
- Can use a dual star topology, by which every normal board connects at 2 switching boards (redundancy).
- Can be used for different serial interconnections, without changes.
- Can use a mesh topology, by which all normal boards interconnect (without a switching board).
- Can use a daisy-chain topology, with the switch board and payload boards connected in a chain.
- Uses normal boards, on which the parallel connectors are replaced by high speed serial connectors.
- Uses payload boards, at which the parallel connectors are replaced with high speed serial connectors.
- Replaces completely the parallel VME bus with serial interconnections.
- Uses a differential clock signal between devices.
With the VME320 bus:
- A source synchronous protocol is used.
- The data transfer protocol uses both edges of the clock signal for data transfers.
- All expansion modules are connected in series.
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