SAP Test 1 Revision

A digital circuit board with various logic gates and flip-flops, illustrating concepts of digital electronics; vibrant colors and clear details

SAP Test 1 Revision Quiz

Test your knowledge and understanding of concepts related to SAP and digital logic design with this comprehensive quiz. This quiz covers topics like flip-flops, state machines, binary numbers, and more, providing an excellent revision tool for students and professionals alike.

Key Features:

Multiple choice questions
Checkbox questions for deeper understanding
Text input for quantitative answers

50 Questions12 MinutesCreated by CodingLogic321

The flip flop setup time is

The time needed to hold the input after the active clock edge

The time for which is the output stable

The time for which the input must be stable before the active clock edge

The time needed to propagate the data from master to the output

Assume a Mealy-type FSM having 2 inputs, 4 outputs, and 3 internal states. The maximum number of different combinations that can appear on the circuit's output is:

The half-adder function can be described as (8 is the sum output, Cout is the carry output, a and b are data inputs)

The MSB carry (carry output from the last stage of the adder) in the 2's complement adder can be used to:

Indicate the sign of the result

To be a carry input to a higher-order adder

Indicate the overflow

An incompletely specified function f(a,b,c,d) where a is the LSB, is given by a list of 1-minterms and don't care minterms: f(d,c,b,a) = summation 1 (2,3,4,10,11,14) + summation x (1,12,13). The minimum SOP of this function is:

Don't cares in a function F description (incompletely specified function)

Arise from flexibility in the behavior specification

Can be assigned any value (0 or 1)

Must be covered in a minimum sum-of-products implementations of F

Must not be covered in a minimum sum-of-products implementations of F

A flip-flop is synchronized by

Control inputs other than clock

Clock edge (rising or falling)

Clock level (0 or 1)

What is the number of flip-flops needed to implement a FSM with 200 states using the binary state encoding? Type just the number, no text is allowed.

What is the range of numbers that can be represented in the sign-magnitude code with a 16-bit number format (M=65536)?

Circuits performing shifts in CPU

Are used for multiplication / division by powers of 2

Use shift registers

Are combinational circuits

An incompletely specified function f(a, b, c, d), where a is the LSB, is given by a list of 1-minterms and don't care-minterms: f(a, b, c, d) = summation 1 (0, 1, 5, 7, 10, 14) + summation z (6, 15). Check correct answers:

B • c is an essential prime implicant of f

B • c is a part of the optimum solution of f

B • c is a prime implicant of f

The optimum solution has 3 terms

Don't cares in a function F description (incompletely specified function)

Must be covered in a minimum sum-of-products implementations of F

Can be assigned any value (0 or 1)

Arise from flexibility in the behavior specification

Must not be covered in a minimum sum-of-products implementations of F

Sequential circuits

Their output depends on their input only

Remember the current state

Their current state depends on the history of the input

What is the number of flip-flops needed to implement a FSM with 10 states using 1 out of N state encoding? Type just the number, no text is allowed.

Overflow in the 2's complement adder is indicated by

The MSB carry bit (carry output from the last stage of the adder)

The MSB sum output bit (sum output from the last stage of the adder)

XORing two last MS output bits (sum outputs from the last two stages of the adder)

XORing two last MSB carry bits (carry outputs from the last two stages of the adder)

Comparison of the signs of the operands and the result

A prime implicant of a function F is

Only a product term that covers a 1-minterm, which is not covered by any other product term

A product term that must be included in all minimum sum-of-products implementations of F

Can be a minterm

An implicant that is not covered by any other implicant

Assume an FSM of type Mealy having 2 inputs, 4 outputs, and 3 internal states. The maximum number of different combinations that can appear on the circuit's output is:

How many inputs and outputs has the half-adder?

3 inputs, 3 outputs

2 inputs, 2 outputs

3 inputs, 2 outputs

2 inputs, 3 outputs

An essential implicant of a function F

Must be a prime implicant

Is a product term that must be included in all minimum sum-of-products implementations of F

Is any product term included in a minimum sum-of-products implementation of F

Is a product term that covers a 1-minterm, which is not covered by any other product term

A prime implicant of a function F is

An implicant that is not covered by any other implicant

Only a product term that covers a 1-minterm, which is not covered by any other product term

Can be a minterm

A product term that must be included in all minimum sum-of-products implementations of F

What is the number of flip-flops needed to implement a FSM with 100 states using 1 out of N state encoding? Type just the number, no text is allowed.

Convert a hexadecimal number OxA8 to binary. Just type the binary string, without any leading characters (i.e., just 0's and 1's).

The flip-flop hold time is

The time needed to propagate the data from master to the output

The time for which the input must be stable before the active clock edge

The time needed to hold the input after the active clock edge

The time for which is the output stable

What is the number of flip-flops needed to implement a FSM with 200 states using 1 out of N state encoding? Type just the number, no text is allowed

Memory organization in Von Neumann's type computer is

Separate memory for code and data

Common memory for code and data

An implicant

Is a product term covering only 1's and possibly also don't cares in a Karnaugh map

Is always a product term containing all variables of the function

Can be a minterm

Asynchronous sequential circuits are synchronized by

Clock edge (rising or falling)

Clock level (0 or 1)

Inputs other than clock (e.g., data)

Assume an FSM of type Mealy having 2 inputs, 4 outputs, and 3 flip-flops. The maximum number of different combinations that can appear on the circuit's output iS:

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SAP Test 1 Revision

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